ASIC Engineer Technical Leader

Cisco SiliconOne team is looking for an expert and talented Senior ASIC Technical Leader. You will have an ASIC development background with hands-on experience in design/dv, post silicon validation, with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products.

Substantial experience in any/all of the following areas is highly desired:

• Microarchitecture and Design
• Implementation of the Chip - Top level design & integration including vendor IPs/PLLs/Serdes/Hard PHYs
• Full Timing constraints - understanding the top-level design and
• developing Timing Constraints, including functional and DFT aspects of timing.
• Analysis of cross clock domain paths at Full chip level and experience with CDC analysis tools.
• Full Chip functional and performance verification
• Document and improve design/dv methodologies to make product successful.

• Worked in micro-architecture and design of high-scale, high-performance ASICs.
• Validated experience in implementation: specification, microarchitecture, design and validation.
• Validated experience in flow automation (scripting, Makefiles, etc), and establishing guidelines for the team.
• Good interpersonal skills, and validated leadership to accurately describe issues and make improvements.
• 12+ years of substantial experience
• Good written/verbal interpersonal skills and leadership skills.

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