Sr. SOC RTL Design Engineer
USA - Arizona - Chandler, USA - Arizona - Tucson, USA - California - California, USA - Texas - Austin
Job Description and Requirements
At Synopsys, we are at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we are powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Our System Design Solutions (SDS) business within Synopsys Solutions Group provides design services related to tool, methodology, design creation, verification, and implementation to enable leading edge customers to complete their most challenging IC design projects. Our customers range from industry leaders to start-ups, developing products for applications such as telecommunications, wireless, broadband, medical, aerospace, automotive, AI, and high-performance computing. We work with customers needing as little as some specific design assistance along a particular skillset to as much as full turnkey designs from specification to parts.
We are looking for a senior SOC RTL design engineer with a specialization in DSP, to join our team.
As a Design Engineer specializing in DSP solutions, you will take on the many aspects of the design development cycle including algorithmic definition and modeling, micro-architectural definition, RTL coding, synthesis, timing closure, and working with verification teams to achieve test closure. In addition, you will be interacting directly with potential customers and Synopsys teams to gather requirements, estimate effort, cost, schedules, design size and feasibility.
Does this sound like a good role for you?
- Work with system engineers to finalize design microarchitecture tradeoffs and algorithm performance
- Implement existing MATLAB/Simulink/C++ models into synthesizable RTL for FPGA and ASICs
- Evaluate tradeoffs between fixed point, block float or floating point-based implementations
- Integrate DSP functions into higher level designs
- Verify RTL designs against existing DSP models
- Proven experience in ASIC/FPGA with emphasis on DSP-based solutions
- Working knowledge of common DSP building blocks and system models
- IIRs, FIRs, polyphase, sampling, decimation, interpolation, DDS, FFT
- Understanding of SV/UVM verification flows
- Experience in bridging of Simulink/MATLAB or C++ models to RTL simulations
- Ability to understand and close on algorithm performance requirements
- BS with 8-10 years relevant experience. MS with 7+ years relevant experience
- Experience with customer interface and collaborative teamwork
- Skilled in scripting languages such as Python, PERL, and TCL
- Knowledge of the Synopsys tools, flows, and methodologies
- Exposure to mixed signals designs and High Speed SerDes
- This position may include assignment to government contracts. Consequently, the ability to obtain government security clearances and/or other work clearances is preferred and will be required in the event of assignment to government contract work
The base salary range across the U.S. for this role is between $133,000 to $232,000. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
Base Salary Range