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Applications Engineering, Staff Engineer

Synopsys
United States, Texas, Austin
February 25, 2024
Staff Applications Engineer - Functional Verification 43568BR USA - Texas - Austin Job Description and Requirements At Synopsys, we are enthusiastic learners and seasoned inventors. We are makers and visionaries who make technology safer. We are innovators who develop the software and hardware that drive the world's high-performing chips for amazing things like autonomous vehicles, smart homes, and machines that learn. We embrace diversity as a company, so we can create solutions that serve not just technology but the humans behind it. The candidate will be a member of the Customer Success Group which offers the industry leading RTL verification platform consisting of multiple technologies. RTL Simulation provides advanced, built-in technologies, including full-featured testbench, complete assertion support, a library of assertion checkers. Also including a comprehensive coverage and analysis, to enable smart verification of complex system-on-chip designs. The Verification IP (VIP) portfolio has complete line of behavioral models, checkers and suite of compliance tests for advanced on-chip protocols. The Formal Verification platform offers static and formal methods that are the best in class. These combined with Hardware Assisted Verification and Emulation Systems create the Synopsys' Verification Platform. Application Engineer (AE) position gives you the opportunity to be part of a fantastic team working on Synopsys Verification Platform, primarily on the simulator, VCS. The responsibilities involve providing pre/post-sales technical support, including analysis of customers' current verification methodologies, presentations and deployment of the next gen ML techniques to accelerate chip development. Desired Skills and Experience BS in CS/EE with 5+ years of experience in functional verification. Knowledge of VLSI design flow and methodology, including HDL/HVL SystemVerilog, Verilog, VHDL, SystemC Experience in front-end verification including RTL/TB coding, simulation debug Working experience on UVM Methodologies Knowledge of Low Power Design/Verification, Debug using Verdi is a plus Proficient in UNIX usage, shell/Perl/YAML scripting Strong communication skills, both verbal and written Ability to lead and coordinate discussions in a small group as well as present to larger groups At Synopsys, we're at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we're powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. Our Silicon Design & Verification business is all about building high-performance silicon chips-faster. We're the world's leading provider of solutions for designing and verifying advanced silicon chips. We enable our customers to optimize chips for power, cost, and performance-eliminating months off their project schedules The base salary range across the U.S. for this role is between $97,000-$169,000. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. #LI-DP1 Job Category Engineering Country United States Job Subcategory Applications Engineering Hire Type Employee Base Salary Range $97,000-$169,000